Symbolic Veriication of Sequential Circuits Synthesized with Callas 1 ; 2 Extended Summary
نویسندگان
چکیده
We present a solution to the veriication problem of high-level synthesis. The high-level synthesis system CALLAS takes as input an algorithmic speciication, in VHDL, and produces as output an EDIF netlist. Both, the speciication and the generated netlist can be interpreted as nite state machine descriptions. Then, in this context, the veriication problem is reduced to proving the behavioral equivalence of both machines. For this equivalence proof we use the symbolic veriier of the CVE System (CVE = Circuit Veriication Environment). Recent improvements of the ve-riier allowed equivalence proofs of machines with up to 260 binary state variables.
منابع مشابه
Probabilistic Symbolic Simulation and Veri cation with -OBDDs
Ordered Binary Decision Diagrams (OBDDs) have already proved useful in the veriication of combinational and sequential circuits. Due to limitations of the descriptive power of OBDDs several more general models of Binary Decision Diagrams have been studied. In this paper,-OBDDs-also known as Mod2OBDDs-in respect to their ability to serve as a tool for combinational veriication are considered. Be...
متن کاملApplications of Fuzzy Program Graph in Symbolic Checking of Fuzzy Flip-Flops
All practical digital circuits are usually a mixture of combinational and sequential logic. Flip–flops are essential to sequential logic therefore fuzzy flip–flops are considered to be among the most essential topics of fuzzy digital circuit. The concept of fuzzy digital circuit is among the most interesting applications of fuzzy sets and logic due to the fact that if there has to be an ultimat...
متن کاملEecient Ordering of State Variables and Transition Relation Partitions in Symbolic Model Checking Eecient Ordering of State Variables and Transition Relation Partitions in Symbolic Model Checking
Among the main algorithmic problems in the veriication of sequential circuits are the computation of good orders of state variables and transition relation partitions. Existing model checking packages like SMV from CMU, VIS from Berkeley or Rulebase from IBM Haifa provide variants of Rudell's sifting algorithm for the variable ordering problem and greedy-type algorithms for the partition orderi...
متن کاملImproving topological ATPG with symbolic techniques
This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...
متن کاملA simple theorem prover based on symbolic trajectory evaluation and BDD's
Formalhardware veriication based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial veriication results is needed. One way of accomplishing this is to use a general purpose theorem prover to combine the veri-cation results obtain...
متن کامل